1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to such a circuit that provides a delay locked loop.
2. Description of the Related Art
Generally, a synchronous dynamic random access memory (SDRAM) receives data in response to an external data input strobe signal and outputs data in response to an internal clock signal which is synchronized by an external clock signal and then generated. Thus, the SDRAM has a delay locked loop to generate an internal clock signal which is locked to the external clock signal.
The delay locked loop should be able to achieve stable operation relative to an external clock signal which has a frequency bandwidth of more than prescribed frequency (hereinafter, high frequency) and a frequency bandwidth of less than prescribed frequency (hereinafter, low frequency). That is, the delay locked loop should be able to tolerate a range of frequencies exhibited by the external clock signal, i.e., it should be able to generate the internal clock signal locked to such a range of possible frequencies of the external clock signal.
FIG. 1 is a block diagram illustrating a conventional delay locked loop 100.
In FIG. 1, the delay locked loop 100 includes a phase detector 110, a delay unit controller 120, and a variable delay unit 130.
Functions of the components of FIG. 1 will be explained below.
The phase detector 110 detects a phase difference between an external clock signal ECLK and an internal clock signal ICLK, and activates an up signal UP or a down signal DN and outputs it. The delay unit controller 120 performs a counting operation to output a control signal CON in response to the up signal UP or the down signal DN outputted from the phase detector 110. The variable delay unit 130 adjusts a delay time of the external clock signal ECLK in response to the control signal CON to generate the internal clock signal ICLK. The variable delay unit 130 repetitively performs the procedure for adjusting a delay time of the external clock signal ECLK in response to the control signal CON until the internal clock signal ICLK becomes locked to the external clock signal ECLK.
FIG. 2 is a block diagram illustrating in more detail the conventional delay unit controller 120 of FIG. 1.
The delay unit controller of FIG. 2 includes a counter 122 and a control signal generating portion 124. Functions of the components of FIG. 2 will be explained below.
The counter 122 increases the bit number of “1” of (or, in other words, increments) a counter output signal CNT when the up signal UP is generated and decreases the bit number of “1” of (or, in other words, decrements) the counter output signal CNT when the down signal DN is generated. For example, in a state that the counter output signal CNT outputted from the counter 122 is “11100000”, the delay unit controller 120 performs an up counting operation to generate a counter output signal CNT of “11110000” when the up signal UP is generated, and performs a down counting operation to generate a counter output signal of “11000000” when the down signal DN is generated.
The control signal generating portion 124 generates the control signal CON in response to the counter output signal CNT. Here, the control signal CON is 8-bit data. Let us assume that the controls signal CON is 8-bit data of con1 to con8. A third upper bit con3 of the control signal becomes “1” when the counter output signal CNT is “11100000”, and a fifth upper bit con5 of the control signal CON becomes “1” when the counter output signal CNT is “11111000”. That is, one bit data of the control signal CON in response to the counter output signal CNT becomes “1”.
FIG. 3 is a block diagram illustrating the conventional variable delay unit 130 of FIG. 1.
The variable delay unit 130 of FIG. 3 includes n delay elements D1 to D(n) and n switch transistors N1 to N(n). In FIG. 3, “OL” denotes an output line for outputting the internal clock signal ICLK, and n-bit data con1 to con(n) represents the control signal CON of FIG. 2.
Referring to FIG. 3, the n delay elements D1 to D(n) are cascade-connected to each other, and the n switch transistors N1 to N(n) are connected between an output of the n delay elements D1 to D(n) and the output line OL.
Functions of the components of FIG. 3 will be explained below.
Each of the n delay elements D1 to D(n) receives the external clock signal ECLK and delays it by a prescribed time. If the delay time of each of the delay elements D1 to D(n) is “Td”, the n-th delay element D(n) delays the external clock signal by n×Td, and the m-th delay element D(m) delays the external clock signal by m×Td. Each of the n switch transistors N1 to N(n) is turned on or off in response to the n-bit data con1 to con(n) to transmit an output signal of a selected one among the n delay elements D1 to D(n) to the output line OL. Here, the output signal transmitted to the output line OL is the internal clock signal CLK.
The variable delay unit 130 of FIG. 3 is designed to include a large number of delay elements so as to tolerate both the external clock signal ECLK of the high frequency and the external clock signal ECLK of the low frequency. Thus, since a large number of delay elements and switch transistors are connected to the output line OL, the output line OL has the heavy load.
When the external clock signal ECLK of the high frequency is applied, a smaller number of delay elements are used compared to when the external clock signal ECLK of the low frequency is applied. The load of the output line OL is the same regardless of the frequency of the external clock signal ECLK. Thus, the load of the output line OL is affected even by the switch transistors and the delay elements which are not used when the external clock signal ECLK of the high frequency is applied.
For example, the m delay elements D1 to D(m) are used when the external clock signal ECLK of the high frequency is applied, whereas all of the n delay elements D1 to D(n) are used when the external clock signal ECLK of the low frequency is applied. Here, m is a natural number which is greater than “1” and less than “n”. Thus, when the external clock signal ECLK of the high frequency is applied, the (n-m) switch transistors N(m+1) to N(n) and the (n-m) delay elements D(m+1) to D(n) which do not operate serve as the load of the output line OL.
The line load is increased because the length of the output line OL is enlarged by the (n-m) delay elements (m+1) to D(n) which are for low frequency operation, and the junction load is increased by the (n-m) switch transistors N(m+1) to N(n) which are for low frequency operation. Meanwhile, the size of a driver which generates a clock signal to an output of the delay element should be increased to stably supply the internal clock signal ICLK when the external clock signal ECLK of the high frequency is applied. It may cause high power consumption as well as increment of the chip size.
FIG. 4 is a block diagram illustrating another conventional delay locked loop 100′. In FIG. 4, the delay locked loop 100′ includes a phase detector 110, a delay unit controller 120′, and a variable delay unit 130′. A function of the phase detector 110 is similar to that of FIG. 1. The delay unit controller 120′ generates a control signal CON by the same method as the delay unit controller 120 of FIG. 1 and generates a selection signal SEL in response to the counter output signal CNT. The variable delay unit 130′ delays the external clock signal ECLK in response to the control signal CON and the selection signal SEL to generate the internal clock signal ICLK locked to the external clock signal ECLK.
FIG. 5 is a block diagram illustrating the conventional delay unit controller 120′ of FIG. 4.
In FIG. 5, the delay unit controller 120′ of FIG. 5 includes a counter 122 and a control signal generating portion 124′. The counter 122 of FIG. 5 is similar in function to that of FIG. 2, and the control signal generating portion 124′ generates the control signal CON by the same method as the control signal generating portion 124 of FIG. 2. The control signal generating portion 124′ generates the selection signal SEL in response to the counter output signal CNT. If the counter output signal CNT comprises n-bit data in which first to m-th bits are used as control signals for both the high frequency and the low frequency and (m+1)-th to n-th bits are used as the control signals only for the low frequency, the selection signal SEL becomes “1” when all of first to m-th bits are “1”, whereas it becomes “0” when all of (m+1)-th to n-th bits are “1”.
FIG. 6 is a block diagram illustrating the conventional variable delay unit 130′ of FIG. 4.
In FIG. 6, the variable delay unit 130′ includes a first variable delay block 132, a second variable delay block 134, and a switch 136. The first variable delay block 132 includes a first group of delay elements D1 to D(m) and a first group of switch transistors N1 to N(m), and the second variable delay block 134 includes a second group of delay elements D(m+1) to D(n) and a second group of switch transistors N(m+1) to N(n). The switch transistors N1 to N(n) are NMOS transistors, and the switch 136 is a PMOS transistor. OL1 and OL2 represent first and second output lines, respectively.
Functions of the components of FIG. 6 will be explained below.
The delay elements D1 to D(n) and the switch transistors N1 to N(m) are similar in function to those of FIG. 3 except for the following. In case where the external clock signal ECLK of the high frequency is applied, when at least one bit data among the first to m-th bit data of the counter output signal CNT is “1”, one bit signal among the control signals con1 to con(m) becomes “1” and the selection signal SEL becomes “1”, so that the switch 136 is turned off. As a result, the first output line OL1 and the second output line OL2 become disconnected from each other, whereby the internal clock signal ICLK is generated through the first output line OL1 and the load of the first output line OL1 is decreased. On the other hand, in case where the external clock signal ECLK of the low frequency is applied, when at least one bit data among the first to m-th bit data of the counter output signal CNT is “1”, one signal among the control signals con1 to con(m) becomes ‘1” and the selection signal SEL becomes “1”, so that the switch 136 is turned off. When at least one bit data among the (m+1)-th to n-th bit data is “1”, one signal among the control signals con(m+1) to con(n) becomes ‘1” and the selection signal SEL becomes “0”, so that the switch 136 is turned on. Thus, when the external clock signal ECLK of the low frequency is applied, the switch 136 is first turned off, so that the first and second output lines OL1 and OL2 become disconnected, and in this state the internal clock signal ICLK is generated through the first output line OL1. Here, when the internal clock signal ICLK and the external clock signal ECLK are not locked to each other, the switch 136 is turned on, so that the first and second output lines OL1 and OL2 become connected together, and thus the internal clock signal ICLK is generated through the first and second output lines OL1 and OL2. That is, when the external clock signal ECLK has the low frequency, the variable delay unit 130′ may have the suddenly increased load of the output line while performing its operation in a state that the load of the output line is decreased.
The variable delay unit 130′ of FIG. 6 has an effect in that the load of the output line is decreased when the external clock signal ECLK has the high frequency. However, when the external clock signal ECLK has the low frequency, the load of the output line is instantly increased when the switch 136 is turned on in response to the selection signal SEL. Thus, a gradient of the internal clock signal ICLK instantly fluctuates, so that a jitter occurs in the internal clock signal ICLK, and it has bad effects on a data window.
Further, when the internal clock signal ICLK locked to the external clock signal ECLK is generated in turn through either of the first and second output lines OL1 and OL2 due to variation in process, voltage and temperature (PVT), the load of the output line often varies. It results in unstable operation of the delay locked loop.